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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. january 1995 copyright ? intel corporation, 1995 order number: 270846-004 87c196kc 16-bit high-performance chmos microcontroller automotive y b 40 cto a 125 c y 16 kbytes of on-chip eprom y 232 byte register file y 256 bytes of additional ram y register-to-register architecture y 28 interrupt sources/16 vectors y peripheral transaction server y 1.75 m s 16 x 16 multiply (16 mhz) y 3.0 m s 32/16 divide (16 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y dynamically configurable 8-bit or 16-bit buswidth y full duplex serial port y high-speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y 3 pulse-width-modulated outputs y four 16-bit software timers y 8- or 10-bit 8-channel a/d converter with sample/hold y hold /hlda bus protocol y otp one-time programmable and qrom versions y available in 12 mhz and 16 mhz versions y 16 mhz operation the 87c196kc 16-bit microcontroller is a high-performance member of the mcs 96 microcontroller family. the 87c196kc is an enhanced 8xc196kb device with 488 bytes ram, 16 mhz operation and 16 kbytes of on-chip eprom. intel's chmos process provides a high performance processor along with low power con- sumption. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter. notice: this datasheet contains information on products in full production. specifications within this datasheet are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
automotive 87c196kc 270846 1 figure 1. 87c196kc block diagram 270846 33 figure 2. the 87c196kc family nomenclature 87c196kc enhanced feature set over the 87c196kb 1. the 87c196kc has twice the ram and twice the eprom of the 87c196kb. also, a vertical register windowing scheme allows the extra 256 bytes of ram to be used as registers. this greatly reduces the context switching time. 2. peripheral transaction server (pts). the pts is an alternative way to service an interrupt, reducing latency and overhead. each interrupt can be mapped to its pts channel, which acts like a dma channel. each interrupt can now do a single or block transfer, without executing an interrupt service routine. special pts modes exist for the a/d converter, hsi, and hso. 3. two extra pulse width modulated outputs. the 87c196kc has added 2 pwm outputs that are functionally compatible to the 87c196kb pwm. 4. timer2 internal clocking. timer2 can now be clocked with an internal source, every 1 or 8 state times. 5. the a/d can now perform an 8- as well as a 10-bit conversion. 8-bit conversion allows for a faster conversion time. 6. additional on-chip memory security. two uprom (uneraseable programmable read only memory) bits can be programmed to disable the bus controller for external code and data fetches. once programmed, a uprom bit cannot be erased. by shutting off the bus controller for external fetches, no one can try and gain access to your code by executing from external memory. 7. new instructions. the 87c196kc has 5 new instructions. an exchange (xchb/xchw) instruction swaps two memory locations, an interruptable block move instruction (bmovi), a table indirect jump (tijmp) instruction, and two instructions for enabling and disabling the pts (epts/dpts). 2
automotive 87c196kc packaging plcc description plcc description plcc description 9 ach7/p0.7 54 ad6/p3.6 31 p1.6/hlda 8 ach6/p0.6 53 ad7/p3.7 30 p1.5/breq 7 ach2/p0.2 52 ad8/p4.0 29 hso.1 6 ach0/p0.0 51 ad9/p4.1 28 hso.0 5 ach1/p0.1 50 ad10/p4.2 27 hso.5/hsi.3 4 ach3/p0.3 49 ad11/p4.3 26 hso.4/hsi.2 3 nmi 48 ad12/p4.4 25 hsi.1 2ea 47 ad13/p4.5 24 hsi.0 1v cc 46 ad14/p4.6 23 p1.4/pwm2 68 v ss 45 ad15/p4.7 22 p1.3/pwm1 67 xtal1 44 t2clk/p2.3 21 p1.2 66 xtal2 43 ready 20 p1.1 65 clkout 42 t2rst/p2.4 19 p1.0 64 buswidth 41 bhe /wrh 18 txd/p2.0 63 inst 40 wr /wrl 17 rxd/p2.1 62 ale/adv 39 pwm0/p2.5 16 reset 61 rd 38 p2.7/t2capture 15 extint/p2.2 60 ad0/p3.0 37 v pp 14 v ss 59 ad1/p3.1 36 v ss 13 v ref 58 ad2/p3.2 35 hso.3 12 angnd 57 ad3/p3.3 34 hso.2 11 ach4/p.04 56 ad4/p3.4 33 p2.6/t2up-dn 10 ach5/p.05 55 ad5/p3.5 32 p1.7/hold figure 3. 68-pin plcc functional pin-out 3
automotive 87c196kc 270846 2 figure 4. 68-pin plcc package table 1. prefix identification plcc 87c196kc AN87C196KC * * otp version 4
automotive 87c196kc pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are three v ss pins, all of which must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp timing pin for the return from powerdown circuit. connect this pin with a 1 m f capacitor to v ss anda1m x resistor to v cc . if this function is not used v pp may be tied to v cc . this pin is the programming voltage on the eprom device. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. reset reset input to the chip. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses and output low for a data fetch. ea input for memory select (external access). ea equal to a ttl-high causes memory accesses to locations 2000h through 5fffh to be directed to on-chip rom/eprom. ea equal to a ttl-low causes accesses to those locations to be directed to off-chip memory. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a signal to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects the bank of memory that is connected to the low byte of the data bus. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe e 1), to the high byte only (a0 e 1, bhe e 0), or both bytes (a0 e 0, bhe e 0). if the wrh function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe /wrh is valid only during 16-bit external memory write cycles. 5
automotive 87c196kc pin descriptions (continued) symbol name and function ready ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. when the external memory is not being used, ready has no effect. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2 and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hsi.3, hso.4 and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. port 0 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions in the 87c196kc. ports 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus. hold bus hold input requesting control of the bus. hlda bus hold acknowledge output indicating release of the bus. breq bus request output activated when the bus controller has a pending external memory cycle. 6
automotive 87c196kc electrical characteristics absolute maximum ratings * ambient temperature under bias b 40 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to a 7.0v power dissipation 0.43w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 4 16 mhz note: angnd and v ss should be nominally at the same potential. dc characteristics (over specified operating conditions) symbol description min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage (note 1) 0.2 v cc a 1.0 v cc a 0.5 v v ih1 input high voltage on xtal 1, ea 0.7 v cc v cc a 0.5 v v ih2 input high voltage on reset 2.2 v cc a 0.5 v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 2.8 ma 1.5 v i ol e 7ma v ol1 output low voltage 0.8 v i ol ea 0.2 ma in reset on p2.5 (note 2) v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a v oh2 output high voltage in reset on 2.0 v i oh eb 0.6 ma p2.0 (note 2) notes: 1. all pins except reset , xtal1 and ea . 2. violating these specifications in reset may cause the part to enter test modes. 7
automotive 87c196kc dc characteristics (over specified operating conditions) symbol description min typ max units test conditions i li input leakage current (std. inputs) g 10 m a0 k v in k v cc b 0.3v i li1 input leakage current (port 0) g 3 m a0 k v in k v ref i tl 1 to 0 transition current (qbd pins) b 650 m av in e 2.0v i il logical 0 input current (qbd pins) b 70 m av in e 0.45v i cc active mode current in reset 50 70 ma xtal1 e 16 mhz i ref a/d converter reference current 2 5 ma v cc e v pp e v ref e 5.5v i idle idle mode current 15 30 ma i pd powerdown mode current 50 t.b.d. m av cc e v pp e v ref e 5.5v r rst reset pullup resistor 6k 65k x v cc e 5.0v, v in e 4.0v c s pin capacitance (any pin to v ss )10pf notes: (notes apply to all specifications) 1. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 2. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0 and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 3. standard inputs include hsi pins, ready, buswidth, nmi, rxd/p2.1, extint/p2.2, t2clk/p2.3 and t2rst/p2.4. 4. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 5. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 6. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst clkout i ol :13ma i oh :13ma 8
automotive 87c196kc 270846 21 i cc max e 3.88 c freq a 8.43 i idle max e 1.65 c freq a 2.2 figure 5. i cc and i idle vs frequency ac characteristics for use over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the system must meet these specifications to work with the 87c196kc: symbol description min max units notes t avyv address valid to ready setup 2 t osc b 75 ns t llyv ale low to ready setup t osc b 70 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2 t osc b 75 ns t llgv ale low to buswidth setup t osc b 60 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (note 2) t rldv rd active to input data valid t osc b 30 ns (note 2) t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc * n, where n e number of wait states. 9
automotive 87c196kc ac characteristics (continued) for use over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the 87c196kc will meet these specifications: symbol description min max units notes f xtal frequency on xtal 1 4.0 16 mhz (note 1) t osc i/f xtal 62.5 250 ns t xhch xtal1 high to clkout high or low 20 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 15 ns t cllh clkout falling edge to ale rising b 515ns t llch ale falling edge to clkout rising b 20 a 15 ns t lhlh ale cycle time 4 t osc ns (note 4) t lhll ale high period t osc b 10 t osc a 10 ns t avll address setup to ale falling edge t osc b 15 t llax address hold after ale falling edge t osc b 40 ns t llrl ale falling edge to rd falling edge t osc b 30 ns t rlcl rd low to clkout falling edge 0 35 ns t rlrh rd low period t osc b 5 ns (note 4) t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 2) t rlaz rd low to address float 5 ns t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 25 ns t qvwh data stable to wr rising edge t osc b 30 (note 4) t chwh clkout high to wr rising edge b 10 15 ns t wlwh wr low period t osc b 30 ns (note 4) t whqx data hold after wr rising edge t osc b 25 ns t whlh wr rising edge to ale rising edge t osc b 10 t osc a 15 ns (note 2) t whbx bhe , inst after wr rising edge t osc b 10 ns t whax ad8 15 hold after wr rising t osc b 30 ns (note 3) t rhbx bhe , inst after rd rising edge t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 30 ns (note 3) notes: 1. testing performed at 4.0 mhz. however, the device is static by design and will typically operate below 1 hz. 2. assuming back-to-back bus cycles. 3. 8-bit bus only. 4. if wait states are used, add 2 t osc * n, where n e number of wait states. 10
automotive 87c196kc system bus timings 270846 22 11
automotive 87c196kc ready timings (one waitstate) 270846 23 buswidth timings 270846 24 12
automotive 87c196kc hold /hlda timings symbol description min max units notes t hvch hold setup 55 ns (note 1) t clhal clkout low to hlda low b 15 15 ns t clbrl clkout low to breq low b 15 15 ns t azhal hlda low to address float 15 ns t bzhal hlda low to bhe , inst, rd ,wr weakly driven 15 ns t clhah clkout low to hlda high b 15 15 ns t clbrh clkout low to breq high b 15 15 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe, inst, rd, wr valid b 10 ns t cllh clkout low to ale high b 515 ns note: 1. to guarantee recognition at next clock. dc specifications in hold min max units weak pullups on adv , rd, 50k 250k v cc e 5.5v, v in e 0.45v wr ,wr l, bhe weak pulldowns on 10k 50k v cc e 5.5v, v in e 2.4 ale, inst 270846 25 13
automotive 87c196kc external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 4.0 16.0 mhz t xlxl oscillator frequency 62.5 250 ns t xhxx high time 22 ns t xlxx low time 22 ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive waveforms 270846 26 an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts-up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications, the capacitance will not exceed 20 pf. ac testing input, output waveforms 270846 27 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 270846 28 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs i ol /i oh e g 15 ma. explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: he high le low ve valid xe no longer valid ze floating signals: ae address be bhe ce clkout de data ge buswidth he hold hae hlda le ale/adv bre breq re rd we wr /wrh /wrl xe xtal1 ye ready qe data out 14
automotive 87c196kc ac characteristicseserial porteshift register mode serial port timingeshift register mode symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge 4 t osc b 50 4 t osc a 50 ns to rising edge (brr t 8002h) t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge 2 t osc b 50 2 t osc a 50 ns to rising edge (brr e 8001h) t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 1 t osc ns waveformeserial porteshift register mode serial port waveformeshift register mode 270846 29 15
automotive 87c196kc eprom specifications ac eprom programming characteristics operating conditions: load capacitance e 150 pf, t a ea 25 c g 5 c, v cc ,v ref e 5v, v ss , angnd e 0v, v pp e 12.50v g 0.25v, ea e 12.50v g 0.25v symbol description min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 50 t osc t avll address setup time 0 t osc t llax address hold time 100 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t plph (2) prog pulse width 50 t osc t phll prog high to next pale low 220 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 220 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc notes: 1. run time programming is done with f osc e 6.0 mhz to 12.0 mhz, v ref e 5v g 0.50v. t a ea 25 cto g 5 c and v pp e 12.50v. for run-time programming over a full operating range, contact the factory. 2. this specification is for the word dump mode. for programming pulses, use 300 t osc a 100 m s. dc eprom programming characteristics symbol description min max units i pp v pp supply current (when programming) 100 ma note: v pp must be within 1v of v cc while v cc k 4.5v. v pp must not have a low impedance path to ground of v ss while v cc l 4.5v. 16
automotive 87c196kc eprom programming waveforms slave programming mode data program mode with single program pulse 270846 30 slave programming mode in word dump with auto increment 270846 31 17
automotive 87c196kc slave programming mode timing in data program with repeated prog pulse and auto increment 270846 32 18
automotive 87c196kc 10-bit a/d characteristics the speed of the a/d converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off. at high frequencies more time is needed for the comparator to settle. the maximum frequency with the clock prescaler disabled is 6 mhz. the conver- sion times with the prescaler turned on or off is shown in the table below. the ad e time register has not been characterized for the 10-bit mode. the converter is ratiometric, so the absolute accura- cy is dependent on the accuracy and stability of v ref .v ref must be close to v cc since it supplies both the resistor ladder and the digital section of the converter. a/d converter specifications the specifications given below assume adherence to the operating conditions section of this data sheet. testing is performed with v ref e 5.12v. clock prescaler on clock prescaler off ioc2.4 e 0 ioc2.4 e 1 156.5 states 89.5 states 19.5 m s @ 16 mhz 29.8 m s @ 6 mhz parameter typical (3) minimum maximum units * notes resolution 1024 1024 levels 10 10 bits absolute error 0 g 4 lsbs full scale error g 3 lsbs zero offset error g 3 lsbs non-linearity 0 g 4 lsbs differential non-linearity error l b 1 a 2 lsbs channel-to-channel matching 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 1, 2 feedthrough b 60 db 1 v cc power supply rejection b 60 db 1 input resistance 750 1.2k x dc input leakage 0 3.0 m a sample time: prescaler on 16 states prescaler off 8 states input capacitance 3 pf notes: * an ``lsb'', as used here, has a value of approximately 5 mv. 1. dc to 100 khz. 2. multiplexer break-before-make guaranteed. 3. typical values are expected for most devices at 25 c. 19
automotive 87c196kc 8-bit mode a/d characteristics the 8-bit mode trades off resolution for a faster con- version time. the ad e time register must be used when performing an 8-bit conversion. the following specifications are tested @ 16 mhz with oa6h in ad e time. the actual ad e time reg- ister is tested with all possible values, to ensure functionality, but the accuracy of the a/d converter is not. sample time convert time 20 states 56 states a6h in ad e time 9.8 m s @ 16 mhz parameter typical minimum maximum units * notes resolution 256 256 levels 8 8 bits absolute error 0 g 2 lsbs full scale error g 1 lsbs zero offset error g 2 lsbs non-linearity 0 g 2 lsbs differential non-linearity error l b 1 a 1 lsbs channel-to-channel matching g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c notes: * an ``lsb'', as used here, has a value of approximately 20 mv. 1. typical values are expected for most devices at 25 c. 8xc196kb to 87c196kc design considerations 1. memory map. the 87c196kc has 512 bytes of ram/sfrs and 16k of rom/eprom. the extra 256 bytes of ram will reside in locations 100h 1ffh and the extra 8k of eprom will reside in locations 4000h 5fffh. these locations are external memory on the 87c196kb. 2. the cde pin on the kb has become a v ss pin on the kc to support 16 mhz operation. 3. eprom programming. the 87c196kc has a dif- ferent programming algorithm to support 16k of on-board memory. when performing run-time programming, use the section of code on page 99 of the 80c196kc user's guide, order num- ber 270704. 4. once mode entry. the once mode is entered on the 87c196kc by driving the txd pin low on the rising edge of reset. the txd pin is held high by a pullup that is specified at 1.4 ma and remain at 2.0v. this pullup must not be overrid- den or the 87c196kc will enter the once mode. 5. during the bus hold state, the 87c196kc weak- ly holds rd, wr, ale, bhe and inst in their inactive states. the 87c196kb only holds ale in its inactive state. 6. a reset pulse from the 87c196kc is 16 states rather than 4 states as on the 87c196kb (i.e., a watchdog timer overflow). this provides a longer reset pulse for other devices in the system. 20
automotive 87c196kc 87c196kc b-3 step errata 1. nmi during pts skips an address: when an nmi interrupts a pts routine, the first byte of the in- struction following completion of the pts cycle is lost. this results in incorrect code execution. workaround: nmi must be disabled using exter- nal hardware during any pts activity. 2. qbd port glitch. there is a strong negative glitch on all qbd port pins (p1.x and p2.6, p2.7) syn- chronous with the first falling edge of clkout. this glitch lasts about 10 ns, and only occurs one time following the initial application of v cc . the time for the pin to return to v cc may be several microseconds, depending on pin loading capaci- tance. workaround: external systems and devic- es should be disabled from responding to this glitch until after the first clkout falling edge has occurred. 3. divide error during hold or ready. the result of a signed divide instruction may be off by one if executed while the device is held off the bus by hold or ready and the queue is empty. specif- ic timings of hold or ready going active or in- active must be met. workaround for hold: dis- able hold during signed divide operations (using hardware or software). workaround for ready: problem will only occur if unlimited wait state mode is selected, and 14 or more wait states are inserted. 4. the hsi unit has two errata: one dealing with res- olution and the other with first entries into the fifo. the hsi resolution is 9 states instead of 8 states. events on the same line may be lost if they occur faster than once every 9 state times. there is a mismatch between the 9 state time hsi resolution and the 8 state time timer. this causes one time value to be unused every 9 timer counts. events may receive a time-tag on one count later than expected because of this ``skipped'' time value. if the first two events into an empty fifo (not including the holding register) occur in the same internal phase, both are recorded with one time- tag. otherwise, if the second event occurs within 9 states after the first, its time-tag is one count later than the first time tag. if this is the ``skipped'' time value, the second event's time-tag is 2 counts later than the first's. if the fifo and holding register are empty, the first event will transfer into the holding register after 8 state times, leaving the fifo empty again. if the second event occurs after this time, it will act as a new first event into an empty fifo. datasheet revision history the following are the key differences between this datasheet and the -003 version: 1. the ``advanced information'' status was dropped and replaced with production status (no label). 2. trademarks were updated. 21

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